High-speed signaling systems use an output buffer driver calibration scheme to reduce timing uncertainty. The need for a calibration scheme is particularly important in bussed systems, where there are several different output buffer drivers that may drive the bus, or where there are several different output buffer drivers that drive a portion of a wide bus. Calibrated output buffer drivers reduce the timing uncertainty by matching the driver output from one output buffer driver to another, by matching the characteristics of a pull up transistor (e.g., a transistor that drives a high voltage) to the characteristics of a pull down transistor (e.g., a transistor that drives a low voltage), by setting an effective output impedance that helps to back-terminate transmission line reflections in the bus system, and by limiting the output voltage slew rates to improve transmittal signal integrity. Some of the benefits obtained by calibrated output buffer drivers can be achieved by closely specifying the driver characteristics for all transistors in an output buffer driver and all output buffer drivers in a system. Techniques such as specifying minimum and maximum output currents, specifying the current versus voltage curves with minimum and maximum limits, and by providing limits on the minimum and maximum slew rates have been used. However, an active calibration scheme can reduce the timing uncertainty further by adjusting out the effects of process variance, voltage variation or temperature variation on output buffer drivers.
In high-speed systems that use parallel bus termination, such as Rambus or SLDRAM, output buffer driver calibration has been implemented by comparing the voltage at the buffer driver output while it is driving high or low, and while the bus is connected through a parallel resistor, to another voltage. The other voltage is often termed VTT, and the VTT voltage level is set by system considerations. The resistor connection to VTT establishes the load current for normal operation, and for the calibration circuit.
In high-speed systems which do not use any form of parallel termination, the proper output buffer driving characteristics are even more critical for reducing timing uncertainty. In these systems, there is no parallel resistor on the bus to terminate the reflections, so the signal integrity relies on the output buffer driver ON impedance to back terminate any reflections in the system. Also, the output buffer driver slew rate can be quite sensitive to the driver characteristics, when there is no DC load provided by a termination resistor.
A calibration scheme has been proposed for non-terminated systems that uses a pull up transistor in an ON state of one output buffer driver as the load to the pull down transistor of a different output buffer driver, and vice versa. However, this will not guarantee that the VOH (logic output high voltage) will be symmetric about a mid-voltage (often called V.sub.Ref) to VOL (logic output low voltage). Rather, this scheme will match the ON resistance of output buffer driver A pull down transistor to the ON resistance of output buffer driver B pull up transistor. Likewise the ON resistance of output buffer driver A's pull up transistor will be calibrated to the ON resistance of output buffer driver B's pull down transistor. If the drive strength of driver B pull up transistor is mismatched to its pull down transistor, then this relationship will be replicated in driver A after calibration. A mismatch of the pull up transistor characteristic with the pull down transistor characteristic will create a different tuning relationship with signals transitioning to a logic one state versus signals transitioning to a logic zero state. This results in a timing uncertainty in the system, which will limit the maximum system operational data rate.
A further limitation of the above approach, is that there are often situations where it is desirable for an output buffer driver at one end of the bus to have a different drive strength than an output buffer driver at the other end of the bus, due to differences in the bus topology that each driver drives. An example of this situation is with a memory controller that drives multiple DRAMs from one end of the bus, and the DRAM which may actually be at an intermediate portion of the bus, as opposed to one end of the bus. With the above calibration scheme, it would not be possible to retain different drive strengths for different output buffer drivers. A final disadvantage of this approach is that there can be risk of device latch-up when two separate drivers drive a bus simultaneously. A driver that has SCR latch up will not allow calibration to occur, and it is usually necessary to remove and re-apply the power supply voltage to exit the latch up condition.